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  • POLYTEDA - Advanced physical verification solutions
    12 16 24 32 CPUs Fastest and most accurate flat engine DRC on the EDA market Un compromising accuracy for all checks simple and complex High performance delivering maximum CPU efficiency per rule check PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm

    Original URL path: http://www.polyteda.com/ (2016-04-26)
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  • POLYTEDA - Advanced physical verification solutions
    12 16 24 32 CPUs Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm Fastest and most accurate flat engine DRC on the EDA market Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service High performance delivering maximum CPU efficiency per rule check Un compromising accuracy for all checks simple and complex

    Original URL path: http://www.polyteda.com/index.php (2016-04-26)
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  • Products
    Scalability proven on 2 4 6 8 12 16 24 32 CPUs Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Fastest and most accurate flat engine DRC on the EDA market Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm Un compromising accuracy for all checks simple and complex PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service High performance

    Original URL path: http://www.polyteda.com/products.html (2016-04-26)
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  • PowerDRC/LVS
    on 2 4 6 8 12 16 24 32 CPUs Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud High performance delivering maximum CPU efficiency per rule check Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm PDF Print E mail PowerDRC LVS POLYTEDA s core product PowerDRC LVS is a tool for the physical verification of microelectronic circuits It enables rapid verification of new designs to ensure accuracy prior to mask creation and manufacturing PowerDRC LVS is unique It can process multiple design rules and design layers simultaneously PowerDRC LVS dramatically reduces design cycle time design iterations compute infrastructure requirements and precious engineering time Customers will benefit from reduced costs and enhanced opportunities to meet aggressive go to market windows In addition to superiority in processing speed PowerDRC LVS can handle huge amounts of data up to tens of billions of transistors It s also compatible with design rule syntaxes from leading competitors allowing customers to port existing design infrastructures to PowerDRC LVS for more efficient processing LVS debug can be very frustrating and can throw a design schedule out by weeks Current debug environments available on the EDA market force the user out

    Original URL path: http://www.polyteda.com/products/powerdrclvs.html (2016-04-26)
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  • PowerRDE
    a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PowerRDE PDF Print E mail PowerRDE is a GUI application that allows user to create DRC LVS or XOR run configuration save it in a run configuration file RCF read a saved configuration run PowerDRC LVS view run progress review results debug violations etc PowerRDE allows to run PowerDRC LVS in multi CPU mode on a single host or multiple hosts controlled by Platform LSF and Oracle Grid Engine SGE PowerRDE can be integrated into Cadence Virtuoso SpringSoft Lake r or KLayout environments with scripts provided in PowerDRC LVS installation package PowerRDE Configure DRC mode main tab PowerRDE View DRC results mode Volations tab PowerRDE Configure LVS mode main tab PowerRDE View LVS results mode Match info tab PowerRDE interoperability with Cadence IC61 highlighting errors in schematic view PowerRDE is a GUI application that allows user to create DRC or LVS run configuration save it in a run configuration file RCF read a saved configuration run PowerDRC LVS view run progress review results debug violations etc PowerRDE allows to run PowerDRC LVS in multi CPU mode on a single host or multiple hosts controlled

    Original URL path: http://www.polyteda.com/products/powerrde.html (2016-04-26)
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  • Demo
    Follow Us Un compromising accuracy for all checks simple and complex High performance delivering maximum CPU efficiency per rule check Scalability proven on 2 4 6 8 12 16 24 32 CPUs PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Fastest and

    Original URL path: http://www.polyteda.com/products/products-demo.html (2016-04-26)
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  • Short Finder component added to PowerDRC/LVS
    1 released PowerDRC LVS 2 0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us Short Finder component added to PowerDRC LVS PDF Print E mail Short Finder is a special utility for graphical LVS debug purposes It delivers the following functionality Suggests a short location Shorted net polygons in a table format Allows to assign label for selected

    Original URL path: http://www.polyteda.com/products/powersf.html (2016-04-26)
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  • Inter-operability
    2 2 released PowerDRC LVS 2 1 released PowerDRC LVS 2 0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PDF Print E mail Inter operability PowerDRC LVS provides inter operability with VENDOR PowerDRC Interface DEMO PowerLVS Interface DEMO Yes View Demo Yes View Demo Yes Planned Planned Planned Yes Planned Yes Planned Yes View Demo Yes View

    Original URL path: http://www.polyteda.com/products/eda-partners.html (2016-04-26)
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