archive-com.com » COM » P » POLYTEDA.COM

Total: 160

Choose link from "Titles, links and description words view":

Or switch to "Titles and links view".
  • POLYTEDA - Advanced physical verification solutions
    Close Window E mail this link to a friend E mail to Sender Your E mail Subject Send Cancel

    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vY29tcGFueS9pbnZlc3RvcnMuaHRtbA%3D%3D (2016-04-26)
    Open archived version from archive



  • TCPDF error Not a JPEG file images stories ihplogo jpg

    Original URL path: http://www.polyteda.com/partners/foundry-partners.pdf (2016-04-26)
    Open archived version from archive

  • Foundry
    PROCESS STATUS Obtain Rule Decks From 180 RF Qualified UMC 180 Pads Qualified UMC 180 ESD Qualified UMC 65 SP Qualified UMC 65 LL Qualified UMC 40 LP Qualified UMC SGB25V TM1TM2 Qualified IHP GmBH SG25 H1H3H3P Qualified IHP GmBH

    Original URL path: http://www.polyteda.com/partners/foundry-partners.html?tmpl=component&print=1&page= (2016-04-26)
    Open archived version from archive

  • POLYTEDA - Advanced physical verification solutions
    Close Window E mail this link to a friend E mail to Sender Your E mail Subject Send Cancel

    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vcGFydG5lcnMvZm91bmRyeS1wYXJ0bmVycy5odG1s (2016-04-26)
    Open archived version from archive

  • Company Partners
    flat engine DRC on the EDA market Un compromising accuracy for all checks simple and complex Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm High performance delivering maximum CPU efficiency per rule check Company Partners At POLYTEDA we believe in providing our customers the flexibility to choose best in class point tools As a result

    Original URL path: http://www.polyteda.com/partners/index.php (2016-04-26)
    Open archived version from archive

  • Industry Organizations
    EDA tool industries We are focused on improving productivity and reducing cost in creating and producing integrated silicon systems We believe that through collaborative efforts the industry can achieve higher levels of systems on silicon integration while reducing the cost and complexity of integrating future design systems Design For Manufacturability Coalition Build the coalition on a strong partnership between Users EDA and Semiconductor suppliers IDM Foundry to capture design manufacturing

    Original URL path: http://www.polyteda.com/partners/industry-organizations.html?tmpl=component&print=1&page= (2016-04-26)
    Open archived version from archive

  • POLYTEDA - Advanced physical verification solutions
    Close Window E mail this link to a friend E mail to Sender Your E mail Subject Send Cancel

    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vcGFydG5lcnMvaW5kdXN0cnktb3JnYW5pemF0aW9ucy5odG1s (2016-04-26)
    Open archived version from archive

  • FAQ
    I re use my rules to work with PowerDRC LVS А PowerDRC LVS doesn t work natively with Calibre or Assura rule files However PWRL rule language of PowerDRC LVS was intentionally made close to SVRF in its semantics and syntax just to facilitate migration Still they are different and certain functional capabilities of PWRL are missing in SVRF For example there are means that let user optimize the process of verification like block command Some complicated checks that require dozens of lines in other languages take as few as couple lines in PWRL Accuracy Q Why should I trust correctness and accuracy of PowerDRC LVS verification А PowerDRC LVS was certified by UMC for 180 65 and 40 nanometers by IHP for 250 and 130 nanometers as well as for many other technologies with silicon proven designs more than 10 permanent customers Q I have an uncommon specific layout file with circles and the like Would that impact accuracy of verification with PowerDRC LVS in any way Any pitfalls to be aware of А No we do not expect problems in such cases Circles are approximated with polygons and PowerDRC LVS supports any angle operations False violations common in approximation may be prevented by proper adjustment of tolerance Performance Q Can I speed up verification by using a multi core CPU system or by adding more RAM modules A Yes you can Our tool can perform DRC verification in multi CPU mode engaging as many available CPU cores as your license and hardware allows Specific acceleration depends on details of your design and the quality of rules Multi CPU mode is not supported for LVS More RAM will not give better performance by itself but it may be useful in multi CPU mode Minimal RAM needed to run PowerDRC LVS is 1GB and recommended is 8GB Q Can I speed up DRC verification by using a multi host system A Yes you can PowerDRC in multi CPU mode readily runs in SGE and LSF grid as well as in NEFELUS cloud environment www nefelus com When verifying a SRAM memory chip on 32 core system in the cloud we got up to 27x acceleration cp single CPU system Q Can I speed up verification by using a GPU A Unfortunately GPU accelaration isn t supported in the current version of PowerDRC LVS Q So how fast is PowerDRC LVS compared to competing tools А On the average PowerDRC LVS is twice as fast as Calibre and 5 6x faster than Assura in single host mode on same design hardware and OS It definitely benefits from having the fastest flat engine on the market under the hood Market positioning and licensing Q What is your license policy А Fairly flexible Most of our customers acquire one year license for certain number of cores with technical support Longer licenses say for 3 years come with considerable discount Some customers don t need verification services for that long and we cut quarterly

    Original URL path: http://www.polyteda.com/faq.html?tmpl=component&print=1&page= (2016-04-26)
    Open archived version from archive



  •