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  • PowerDRC/LVS version 1.5.2 released
    below for DRC and 130nm and above for LVS with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique Foundry Support During beta test period POLYTEDA worked with leading Asian

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/144-powerdrc-lvs-152-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • PowerDRC UMC40nm LP ver. 1.1 certified
    Mode Low Power Process ver 1 1 New version 1 1 of DRC rule decks set for UMC 40 nm Low Power Process including memory rules was validated by using PowerDRC LVS general availability 1 5 1 release and are available on UMC s web site for fab s customers About POLYTEDA POLYTEDA Software Corporation is a provider of One Shot DRC processing within its Fine Grain Physical Verification fgPV

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/147-powerdrc-umc40nm-lp-ver-11-certified.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • PowerDRC/LVS version 1.5.1 released
    times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique Foundry Support During the Beta test period POLYTEDA worked with leading Asian foundries to validate accuracy and performance for production Contact us

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/143-powerdrc-lvs-151-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • Power DRC: Influential EDA blogger on how it is differentiated
    Power DRC Influential EDA blogger on how it is differentiated Tuesday 29 June 2010 00 00 Power DRC Influential EDA blogger on how it is differentiated Read more on EDN

    Original URL path: http://www.polyteda.com/news-a-events/news/119-power-drc-influential-eda-blogger-on-how-it-is-differentiated-.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • EDA Startup Tops Gary Smith’s Must-See List
    of modern complex designs Cooperation with the National Technical University of Ukraine provides scientific support for product development and the company has software development contracts with companies in Moscow and in Minsk in Belorussia The company launched its first product an IC layout processing utility called PowerLPU in July 2007 Its second product for layout versus schematic and design rule checking called PowerDRC LVS was announced in December 2008 along

    Original URL path: http://www.polyteda.com/news-a-events/news/74-eda-startup-tops-gary-smiths-must-see-list.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • POLYTEDA Makes John Cooley’s “My Cheesy Must-See for DAC 2009”
    ERCs like ESD checks using both netlist and layout based rules booth 3567 Ask for Carey Robertson Magma Quartz DRC LVS are 3X 10X faster and NOW offers Direct Read of Calibre runsets making Quartz the must see for DRC LVS Customers include TSMC IBM Nvidia Toshiba Samsung and Chartered booth 1414 Ask for John Lee Freebie pens For DRC LVS Synopsys is de emphasizing Hercules to force users to their new IC Validator DRC LVS Upside ICV works fast inside ICC Downside confusion whether ICV works outside of ICC Toshiba and Nvidia use it booth 1120 Ask for Rahul Kapoor Freebie none New to DAC Micrologic VisualDRC imports the signoff DRC rules into Virtuoso or Laker checking the rules on the fly with visual feedback enabling correct by construction layout Shortens layout by 40 50 booth 3259 Ask for Danny Rittman Freebie none New to DAC PolyTEDA PowerDRC is an edge based Design Rule Checker for those looking for a good alternative to Calibre or Hercules booth 814 Ask for Mike Zatezalo Freebie flashlight screwdriver 10 In so called Intelligent Testbenches Springsoft s Certitude which they got when they acquired Certess last year injects bugs into your design to see if your current testbench catches them Intel ST SanDisk Ericsson Broadcom uses them booth 3367 Ask for Jean Marc Forey Freebie 2 GB flash drive Nusym Denibulator does the same thing but also analysis to directly build insight into the specified coverage points and provide the test vectors needed to hit them Qualcomm uses Nusym booth 622 Ask for Alex Sibelescu Freebie protein bars 11 For clock domain crossing bugs Real Intent pimps Meridian CDC It handles free running clocks hierarchy and messy FIFOs booth 1728 Ask for Prakash Narain Freebie back packs Jasper JasperCore allows users to cheaply implement multiple proofs and applications across multiple cores and computers efficiently serving multiple users even across multiple business units booth 3767 Ask for Rajeev Ranjan Freebie 1 GB flash drives OneSpin 360 MV is a family of tools for formal assertion based verification from early automatic RTL analysis and block level verification all the way to System Verilog Assertions SVA booth 3465 Ask for Michael Siegel Freebie puzzle 12 EVE ZeBu Server is a scalable emulation system expandable to one billion ASIC equivalent gates That s 1 000 000 0000 Use multi user multi mode at 10 MHz on a 10 million gate design Compile 1 B gates at a rate of 100 M ASIC gates per hour on a PC farm Users are Apple AMD Broadcom Fujitsu Intel LSI Marvell NEC Northrop Grumman NXP Qualcomm Renesas Sanyo ST TI Toshiba booth 908 Ask for Lauro Rizzatti Freebie money clips Synopsys Synplicity HAPS is an Altera Stratix III FPGA prototyping board for high performance simulation and validation After validation the same model can be used with the Synplify DSP tool to explore architectural optimizations and automate handoff to ASIC booth 1120 Ask for Doug Johnson or Chris Eddington No freebie The Dini Group has a new Altera Stratix IV protoboard and they re starting to ship Xilinx Virtex 6 booth 1878 Ask for Mike Dini 13 For analog mixed signal tools Pulsic Unity does placement routing hierarchical floorplanning editing SI ECO and timing analysis for mixed A D anything non ASIC Reads Writes CDBA DFII LEF DEF OA Spice CDL SDC Verilog lib etc you name it we do it Used by SanDisk Altera Samsung Hynix Toshiba Oki NEC Sony Micron booth 815 Ask for Mark Waller or Steve Ferguson Freebie pen Ciranova Helix does AMS floorplanning and placement concurrent trial routing for parasitics TSMC iPDK used on designs over 40 K xistors booth 4400 Ask for Dave Millman Freebie LED flashlights Apache Totem is a layout driven full chip transistor level power integrity and substrate noise analysis tool It expands our power and noise product offering from SoC digital to AMS designs booth 722 Ask for Aveek Sarkar Freebie stuffed polar bear New to DAC Mephisto M Design does AMS IP creation verification documentation and migration at different abstraction levels booth 521 Ask for Kenneth Francken Freebie clocks 14 Tanner EDA HiPer PX extracts interconnect parasitics and produces an RC finite element model for simulation Extraction can be performed using 2D table interpolation or a boundary element 3D field solver booth 3655 Ask for Jeff Miller Freebie travel playing cards Magwel Power Transistor Modeler extracts resistance and displays hot spots in large power transistor arrays with 3D accuracy booth 3357 Ask for Mike Stuber or Dundar Dumlugol No freebie New to DAC Silicon Frontline F3D and R3D does parasitic extraction with lots of vague claims booth 3165 Ask for Yuri Feinberg 15 For constrant tools FishTail Focus now merges multi mode SDC files into a single super mode constraint file which cuts STA and P R runtime drastically TI is presenting on this tool Like Atrenta below FishTail ReFocus also does EC on constraints now too booth 3064 Ask for Ajay Daga Freebie nothing In this same space Real Intent PureTime also sniffs your SDC Tcl constraints for set false path and set multicycle path issues booth 1728 Ask for Prakash Narain Freebie wine glasses Atrenta SpyGlass Constraints does equivalence checking this year for constraints and designs at various stages like RTL netlist pre layout post layout Renesas ST Samsung use this tool booth 1528 Ask for Ron Craig Freebie card trick and t shirts 16 This year in floorplaning Magma Hydra now supports channel style near abutment and full abutment plus automated partitioning shaping macro placement and pin assignment A bunch of companies use Hydra ClearSpeed Renesas Texas Instruments eSilicon Uniquify ARM Open Silicon STARC Toshiba booth 1414 Ask for Rob Knoth I ve heard the Mentor Sierra folks are working on Project Tetris to add 100 M gate capacity floorplanning chip assembly and chip finishing to Olympus SoC booth 3567 Ask for Sudhakar Jilla Atoptech Apogee does topdown chip planning partitioning bottom up chip assembly and chip

    Original URL path: http://www.polyteda.com/news-a-events/news/75-polyteda-makes-john-cooleys-my-cheesy-must-see-for-dac-2009.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • KLayout integration
    shorted nets using POLYTEDA Short Finder utility T he integration requires that the source code of K Layout should be changed to allow for running PowerDRC LVS and for debugging of highlighted violations To use this feature you need to download KLayout 0 23 11 specifically modified by POLYTEDA You can download the binary and source code of the modified version of KLayout free as required by GPL from this

    Original URL path: http://www.polyteda.com/products/52-powerlvs/154-klayout-integration.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • PowerLVS
    University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm Fastest and most accurate flat engine DRC on the EDA market PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service Scalability proven on 2 4 6 8 12 16 24 32 CPUs Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS

    Original URL path: http://www.polyteda.com/products/52-powerlvs/index.php (2016-04-26)
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