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  • Company
    2 1 released PowerDRC LVS 2 0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Fastest and most accurate flat engine DRC on the EDA market Un compromising accuracy for all checks simple and complex Scalability proven on 2 4 6 8 12 16 24 32 CPUs High performance delivering maximum CPU efficiency per rule check Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm POLYTEDA was established in 2005 in Toronto Canada Since 2009 it is privately held by KM Core and headquartered in Kiev Ukraine POLYTEDA has built an outstanding team of professionals from the EDA industry Our engineers have superior experience in developing high end software for the microelectronics industry Our management team has a strong background in EDA We are supported by our R D facility in Kiev Ukraine and with scientific support for product development provided by the National Technical University in Kiev We partner with leading design automation companies to enhance customer value through intelligent

    Original URL path: http://www.polyteda.com/company.html (2016-04-26)
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  • Management
    Alexander is co founder of Genesys Ltd he has 12 years of experience in the Microelectronics industry and 8 years expertise in memory compilers development Graduated from Kiev Polytechnic University in 2007 with Magister degree of Instrument building has 5 scientific publications and 3 patents During 5 years 2008 2013 Alexander has had a perfect career as professional HW benchmarker PC hardware extreme overclocking Dr Nikolay B Grudanov Director of R D and Main Advisor Nikolay is CEO and founder of Genesys Ltd he has more than 35 years of experience in the Microelectronics industry Previously he held position Director of Science in R D Institute of Microdevices one of the most famous former USSR semiconductor company and has more than 50 scientific papers and publications 12 patents Nikolay graduated from Kiev Polytechnic University in 1974 with Masters degree in Electronic Engineering Igor Lopanenko CTO and Co Founder Igor Lopanenko Chief Scientist and co founder of POLYTEDA has more than 35 years of experience in the EDA industry Together with Vlad Marchuk he co founded the OTTO Software Company After acquisition of the company by Cadence Design Systems and up until May 2006 Igor worked as a Senior Application Architect

    Original URL path: http://www.polyteda.com/company/management1.html (2016-04-26)
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  • Careers
    News Company Management Careers Investors Partners Foundry Partners Industry Organizations FAQ Contact Us Submit Request Featured News PowerDRC LVS 2 2 released PowerDRC LVS 2 1 released PowerDRC LVS 2 0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PDF Print E mail Careers There are currently no vacancies available Useful Information Download PowerDRC LVS benchmark results Download

    Original URL path: http://www.polyteda.com/company/careers.html (2016-04-26)
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  • Investors
    1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Fastest and most accurate flat engine DRC on the EDA market PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service High performance delivering maximum CPU efficiency per rule check Un compromising accuracy for all checks simple and complex Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm Scalability proven on 2 4 6 8 12 16 24 32 CPUs PDF Print E mail Investors In addition to the founders and some small individual investors the primary funding for the company has been provided by KM Core КМ Core KM Core technology investment company manages the portfolio of eleven high tech businesses based in various parts of the world namely in Ukraine Russia the United States Canada and Israel KM Core develops high technologies globally by combining the rich intellectual capital of Eastern Europe with the world s leading knowledge and experience The investment portfolio of KM Core includes companies working in the following fields Info communicative technologies KM Ware KM Techno De

    Original URL path: http://www.polyteda.com/company/investors.html (2016-04-26)
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  • Company Partners
    Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Fastest and most accurate flat engine DRC on the EDA market PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service Un compromising accuracy for all checks simple and complex Company Partners At POLYTEDA we believe in providing our customers the flexibility to choose best in class point tools As a result

    Original URL path: http://www.polyteda.com/partners.html (2016-04-26)
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  • Foundry
    0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PDF Print E mail Foundry Partners Here is a snap shot of our current Foundry Support FOUNDRY PROCESS STATUS Obtain Rule Decks From 180 RF Qualified UMC 180 Pads Qualified UMC 180 ESD Qualified UMC 65 SP Qualified UMC 65 LL Qualified UMC 40 LP Qualified UMC SGB25V TM1TM2

    Original URL path: http://www.polyteda.com/partners/foundry-partners.html (2016-04-26)
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  • Industry Organizations
    Industry Organizations Here is a summary of our current partners The Electronic Design Automation Consortium is the international association of companies developing EDA tools and services that enable engineers to create the world s electronic products The EDA Industry provides the critical technology to design electronics that enable the Information Age including communications computers space technology medical and industrial equipment and consumer electronics Please visit EDAC to get more information EDAC Silicon Integration Initiative Si2 is an organization of industry leading companies in the semiconductor electronic systems and EDA tool industries We are focused on improving productivity and reducing cost in creating and producing integrated silicon systems We believe that through collaborative efforts the industry can achieve higher levels of systems on silicon integration while reducing the cost and complexity of integrating future design systems Design For Manufacturability Coalition Build the coalition on a strong partnership between Users EDA and Semiconductor suppliers IDM Foundry to capture design manufacturing requirements prioritizing and formalizing them into Open Solutions In addition the coalition helps expand cross industry DFM DFY awareness through reports testimonials workshops events etc and form alliances with consortia in other parts of the supply chain Thousands of IC and system

    Original URL path: http://www.polyteda.com/partners/industry-organizations.html (2016-04-26)
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  • FAQ
    special option which tells the program to recognize memory cells as hierarchical units during extraction Q What formats of input and output data are supported in PowerDRC LVS А It is GDSII and OASIS for layout and CDL SPICE Verilog for schematic OpenAccess for schematic and layout is only supported in integration with Cadence IC61 through their built in convertor Q Can I re use my rules to work with PowerDRC LVS А PowerDRC LVS doesn t work natively with Calibre or Assura rule files However PWRL rule language of PowerDRC LVS was intentionally made close to SVRF in its semantics and syntax just to facilitate migration Still they are different and certain functional capabilities of PWRL are missing in SVRF For example there are means that let user optimize the process of verification like block command Some complicated checks that require dozens of lines in other languages take as few as couple lines in PWRL Accuracy Q Why should I trust correctness and accuracy of PowerDRC LVS verification А PowerDRC LVS was certified by UMC for 180 65 and 40 nanometers by IHP for 250 and 130 nanometers as well as for many other technologies with silicon proven designs more than 10 permanent customers Q I have an uncommon specific layout file with circles and the like Would that impact accuracy of verification with PowerDRC LVS in any way Any pitfalls to be aware of А No we do not expect problems in such cases Circles are approximated with polygons and PowerDRC LVS supports any angle operations False violations common in approximation may be prevented by proper adjustment of tolerance Performance Q Can I speed up verification by using a multi core CPU system or by adding more RAM modules A Yes you can Our tool can perform DRC verification in multi CPU mode engaging as many available CPU cores as your license and hardware allows Specific acceleration depends on details of your design and the quality of rules Multi CPU mode is not supported for LVS More RAM will not give better performance by itself but it may be useful in multi CPU mode Minimal RAM needed to run PowerDRC LVS is 1GB and recommended is 8GB Q Can I speed up DRC verification by using a multi host system A Yes you can PowerDRC in multi CPU mode readily runs in SGE and LSF grid as well as in NEFELUS cloud environment www nefelus com When verifying a SRAM memory chip on 32 core system in the cloud we got up to 27x acceleration cp single CPU system Q Can I speed up verification by using a GPU A Unfortunately GPU accelaration isn t supported in the current version of PowerDRC LVS Q So how fast is PowerDRC LVS compared to competing tools А On the average PowerDRC LVS is twice as fast as Calibre and 5 6x faster than Assura in single host mode on same design hardware and OS It definitely benefits from having the

    Original URL path: http://www.polyteda.com/faq.html (2016-04-26)
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