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  • Contact Us
    teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PowerDRC LVS is available on NEFELUS Cloud Platform as pay per use service Multi CPU operations for linear performance gain on a single host LSF SGE NEFELUS cloud Un compromising accuracy for all checks simple and complex Fastest and most accurate flat engine DRC on the EDA market High performance delivering maximum CPU efficiency per rule check Silicon proven 250nm 180nm 130nm 90nm 65nm 40nm Scalability proven on 2 4 6 8 12 16 24 32 CPUs Contact Us Headquarter and R D UKRAINE POLYTEDA Ukraine LLC Kiev 04136 1 3 Pyvnichno Syretska st Alexander Grudanov Tel 380 44 200 42 08 This e mail address is being protected from spambots You need JavaScript enabled to view it Sales NORTH AMERICA TekStart LLC 3945 Freedom Circle Suite 320 Santa Clara CA 95054 USA Tel 408 317 0890 Sales This e mail address is being protected from spambots You need JavaScript enabled to view it Tel 650 461 9194 Marketing This e mail address is being protected from spambots You need JavaScript enabled to view it Tel 408 826 1255 EUROPE and ISRAEL TekStart LLC A

    Original URL path: http://www.polyteda.com/contact-us.html (2016-04-26)
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  • Online Request Form
    Print E mail Online Request Form First name Last name E mail Your position Company name Company size staff 1 10 10 50 50 100 100 and above Web site Web site start from http example http www google com Which product are you interested in DRC LVS Both Which design environment do you use Cadence Virtuoso SpringSoft Laker KLayout Other tool Grid support required Operating system Windows 32 bit

    Original URL path: http://www.polyteda.com/contact-us/submitrequest.html (2016-04-26)
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  • PowerDRC/LVS 2.2 released
    to delivering fill layer generation for multi CPU mode new KLayout integration functionality and other significant improvements for multi CPU mode Added support of hierarchical fill layers output Upgraded the supported version of KLayout to 0 23 11 In hierarchical mode of PowerDRC LVS added automatic switching of cells during highlighting in KLayout Added highlight color selection for KLayout Added support of Symica DE Windows 32 bit only In PowerRDE added highlighting of the errors found during device net extraction Added AllowDuplicatedCells RCF parameter to control merging of the layout file with the earlier saved fill layers Added support of network paths for rule files Improved memory management for single CPU mode where preprocessing now is performed in all cases to free memory for the DRC stage Improved the behavior of restart and assembly commands Improved detection of CPU parameters for Windows OS Improved readability of PowerDRC LVS logs and summary Improved tooltips in PowerRDE Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and native window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production on real designs Foundry Support This e mail address is being protected from spambots You need JavaScript enabled to view it to learn more about the availability of foundry rule decks Availability The release version is officially available from POLYTEDA Contact This

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/167-powerdrclvs-22-released.html (2016-04-26)
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  • PowerDRC/LVS 2.1 released
    release is dedicated to delivering new DRC functionality and further significant improvements for multi CPU mode Added support of hierarchical mode for multi CPU configurations Improved errors highlighting and switching between cells in PowerRDE in hierarchical mode New QuickDiff capability a quick check for changes by means of special heuristic algorithms It is intended primarily to detect differences or ensure their absence in two revisions of a given layout close to tapeout QuickDiff may be used as pre processing stage for XOR resulting in dramatic speedup of XOR operation New LVL licenses cover both XOR and QuickDiff capabilities Considerably improved PowerRDE usability Improved readability of PowerDRC LVS logs and summary Improved handling of critical situations for multi CPU mode Added MaxHaloForStripMode RCF para meter for more control over parallelism efficiency and StripInfoLayer to assign layer for information on strips geometry Added StripOverheadThreshold RCF parameter to improve control over strip parallelism overhead in grid invorinment Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and tive window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production Foundry Support This e mail address is being protected from spambots You need JavaScript enabled to view it to learn more about the availability of foundry rule decks Availability The release version is officially available from POLYTEDA Contact This e mail address is

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/166-powerdrclvs-21-released.html (2016-04-26)
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  • PowerDRC/LVS 2.0.1 released
    allows to report upper layer polygons that get conflicting connectivity Added support of with text command for hierarchical mode of LVS XOR capability improvements Added support of multi CPU to dramatically improve XOR performance XOR mode became a separately licensed feature Improved handling of critical situations Added support of OA and CDBA formats when XOR is started from PowerRDE application Improved readability of PowerDRC LVS logs and summary Discontinued support of Linux 4 by PowerDRC LVS Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and tive window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production Foundry Support This e mail address is being protected from spambots You need JavaScript enabled to view it to learn more

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/162-powerdrclvs-201-released.html (2016-04-26)
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  • POLYTEDA donated a teaching license to University of Roma Tor Vergata
    2 0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us POLYTEDA donated a teaching license to University of Roma Tor Vergata Thursday 13 November 2014 00 00 POLYTEDA LLC donated a teaching license for 1 seat of its PowerDRC LVS flagship product to University of Roma Tor Vergata Italy to be used with Analog Office from AWR Corp

    Original URL path: http://www.polyteda.com/news-a-events/news/156-polyteda-donated-a-teaching-license-to-university-of-roma-tor-tergata.html (2016-04-26)
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  • PowerDRC/LVS 2.0 released
    major new version brings new powerful functionality and considerably enhanced performance New algorithms of parallel processing in PowerDRC expand parallelism from rules to layout thus dramatically enhancing scalability to 16 32 64 and more CPUs Also parallelism is now fully supported on all platforms supported by PowerDRC LVS including Windows Added new capabilities and improved usability of PowerRDE Now you can simultaneously highlight all errors of the same type Error visualization was added for the hierarchical mode of DRC Now you can separately define top cells for schematic and layout It got new controls and new tabs for interim logs of new parallel processing Revised and improved PowerDRC LVS operation in a cloud environment Added IgnoreCells command for explicit listing of cells to ignore Improved PowerNVN behavior with many options Improved readability of PowerDRC LVS logs and summ ary Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and tive window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production Foundry Support This e mail address is being protected from spambots You need JavaScript enabled to view it to learn more about the availability of foundry rule decks Availability and Demonstration Pre release of PowerDRC LVS 2 0 was successfully presented in San Francisco at DAC2014 and now the release version is officially available from POLYTEDA Contact This e

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/161-powerdrclvs-20-released.html (2016-04-26)
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  • AWR DRC Demo
    LVS 2 1 released PowerDRC LVS 2 0 1 released POLYTEDA donated a teaching license to University of Roma Tor Vergata PowerDRC LVS 2 0 released Follow Us PDF Print E mail This is a demo of POLYTEDA s PowerDRC integrated with AWR s Analog Office suite For more information contact This e mail address is being protected from spambots You need JavaScript enabled to view it For information on

    Original URL path: http://www.polyteda.com/powerdrc-demo.html (2016-04-26)
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