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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vdGVjaG5vbG9neS9maWxsLWxheWVycy1nZW5lcmF0aW9uLmh0bWw%3D (2016-04-26)
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  • PowerDRC/LVS 2.2 released
    highlighting of the errors found during device net extraction Added AllowDuplicatedCells RCF parameter to control merging of the layout file with the earlier saved fill layers Added support of network paths for rule files Improved memory management for single CPU mode where preprocessing now is performed in all cases to free memory for the DRC stage Improved the behavior of restart and assembly commands Improved detection of CPU parameters for Windows OS Improved readability of PowerDRC LVS logs and summary Improved tooltips in PowerRDE Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and native window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production on real designs Foundry Support This e mail address is being protected from

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/167-powerdrclvs-22-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vbmV3cy1hLWV2ZW50cy9wcmVzcy1yZWxlYXNlcy8xNjctcG93ZXJkcmNsdnMtMjItcmVsZWFzZWQuaHRtbA%3D%3D (2016-04-26)
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  • PowerDRC/LVS 2.1 released
    QuickDiff may be used as pre processing stage for XOR resulting in dramatic speedup of XOR operation New LVL licenses cover both XOR and QuickDiff capabilities Considerably improved PowerRDE usability Improved readability of PowerDRC LVS logs and summary Improved handling of critical situations for multi CPU mode Added MaxHaloForStripMode RCF para meter for more control over parallelism efficiency and StripInfoLayer to assign layer for information on strips geometry Added StripOverheadThreshold RCF parameter to improve control over strip parallelism overhead in grid invorinment Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and tive window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production Foundry Support This e mail address is being protected from spambots You need JavaScript enabled

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/166-powerdrclvs-21-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vbmV3cy1hLWV2ZW50cy9wcmVzcy1yZWxlYXNlcy8xNjYtcG93ZXJkcmNsdnMtMjEtcmVsZWFzZWQuaHRtbA%3D%3D (2016-04-26)
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  • PowerDRC/LVS 2.0.1 released
    XOR capability improvements Added support of multi CPU to dramatically improve XOR performance XOR mode became a separately licensed feature Improved handling of critical situations Added support of OA and CDBA formats when XOR is started from PowerRDE application Improved readability of PowerDRC LVS logs and summary Discontinued support of Linux 4 by PowerDRC LVS Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and tive window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production Foundry Support This e mail address is being protected from spambots You need JavaScript enabled to view it to learn more about the availability of foundry rule decks Availability The release version is officially available from POLYTEDA Contact This e mail address

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/162-powerdrclvs-201-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vbmV3cy1hLWV2ZW50cy9wcmVzcy1yZWxlYXNlcy8xNjItcG93ZXJkcmNsdnMtMjAxLXJlbGVhc2VkLmh0bWw%3D (2016-04-26)
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  • PowerDRC/LVS 2.0 released
    added for the hierarchical mode of DRC Now you can separately define top cells for schematic and layout It got new controls and new tabs for interim logs of new parallel processing Revised and improved PowerDRC LVS operation in a cloud environment Added IgnoreCells command for explicit listing of cells to ignore Improved PowerNVN behavior with many options Improved readability of PowerDRC LVS logs and summ ary Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and tive window scanning technique Production Quality During beta test period POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production Foundry Support This e mail address is being protected from spambots You need JavaScript enabled to view it to learn more about the availability of foundry rule decks Availability and Demonstration

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/161-powerdrclvs-20-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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