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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vbmV3cy1hLWV2ZW50cy9wcmVzcy1yZWxlYXNlcy8xNjEtcG93ZXJkcmNsdnMtMjAtcmVsZWFzZWQuaHRtbA%3D%3D (2016-04-26)
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  • PowerDRC/LVS 1.7.1 released
    LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique Foundry Support

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/159-powerdrclvs-171-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vbmV3cy1hLWV2ZW50cy9wcmVzcy1yZWxlYXNlcy8xNTktcG93ZXJkcmNsdnMtMTcxLXJlbGVhc2VkLmh0bWw%3D (2016-04-26)
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  • PowerDRC/LVS 1.7.1 released
    design software today announced the general availability of PowerDRC LVS version 1 7 1 This release is dedicated to delivering new functionality Support of fill operation was added in PowerDRC allowing to create an array of rectangles of specified dimensions and spacing for use in dummy fill creation ParDRC work in the hierarchical mode was improved PowerRDE got four controls for Hierarchical mode and two more controls for explicit listing of flat and hierarchical cells in Extraction mode Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes up to 40nm with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique Foundry Support During beta test period POLYTEDA worked with wilde list of partners and evaluators to validate accuracy and performance for production Contact us to learn more about the availability of foundry rule decks Availability and Demonstration PowerDRC LVS 1 7 1 is available now from

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/159-powerdrclvs-171-released.html (2016-04-26)
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  • PowerDRC/LVS 1.7 released
    those chips that have macroblocks PowerRDE is now available for the Windows platform PowerRDE now can be integrated with KLayout viewer and editor to perform DRC run and debug Some functional enhancements in LVS functionality More convenient XOR Starting from this version you can benefit from using PowerLVS Short Finder that is a GUI application for finding shorted nets quickly Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes 4 0nm and below for DRC and 130nm and above for LVS with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique Foundry Support During beta test period POLYTEDA worked with wilde list of partners and evaluators to validate accuracy and performance for production Contact us to learn more about the availability of foundry rule decks Availability and Demonstration PowerDRC LVS 1 7 is available now from POLYTEDA Contact This e mail address is being protected from

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/155-powerdrclvs-17-released.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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  • POLYTEDA - Advanced physical verification solutions
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    Original URL path: http://www.polyteda.com/component/mailto/?tmpl=component&link=aHR0cDovL3d3dy5wb2x5dGVkYS5jb20vbmV3cy1hLWV2ZW50cy9wcmVzcy1yZWxlYXNlcy8xNTUtcG93ZXJkcmNsdnMtMTctcmVsZWFzZWQuaHRtbA%3D%3D (2016-04-26)
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  • PowerDRC/LVS 1.7 released
    1 7 This release is dedicated to delivering new functionality Hierarchical Mode is added in PowerDRC allowing to increase performance dramatically for those chips that have macroblocks PowerRDE is now available for the Windows platform PowerRDE now can be integrated with KLayout viewer and editor to perform DRC run and debug Some functional enhancements in LVS functionality More convenient XOR Starting from this version you can benefit from using PowerLVS Short Finder that is a GUI application for finding shorted nets quickly Please review Release Notes for more information PowerDRC LVS is designed to process integrated circuit IC designs of various size at technology nodes 4 0nm and below for DRC and 130nm and above for LVS with run times which are fast and completely predictable It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions PowerDRC LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique Foundry Support During beta test period POLYTEDA worked with wilde list of partners and evaluators to validate accuracy and performance for production Contact us to learn more about the availability of foundry rule

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/155-powerdrclvs-17-released.html (2016-04-26)
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  • POLYTEDA to Expand Global Activities Through New Joint Alliance with TekStart
    a position to take advantage of POLYTEDA s intimate knowledge of the challenges faced by our advanced SoC and Foundry customers The One Shot DRC processing platform help deliver the required accuracy unparalleled capacity scaling and runtime performance these customers expect said Howard Pakosh President and Chief Executive Officer TekStart By officially recognizing this partnership we are continuing to grow our capabilities and services giving our customers the tools necessary to develop next generation technologies POLYTEDA is happy to team with TekStart Their expertise and portfolio is complementary to ours so we expect that our customers can gain significant synergies from this cooperation comments POLYTEDA s Deputy Director of Engineering Alexander Grudanov POLYTEDA has been shipping product for five years and is actively working with advanced foundries engaged in delivering the One Shot DRC based fgPV technology platform on a worldwide basis Customers are seeing accurate results with significant gains in performance and capacity at advanced sub wavelength process nodes TekStart will promote and support POLYTEDA s PowerDRC LVS PV to semiconductor communities through its channel of associates in North America Europe Israel Japan Taiwan ROC and China PRC with a specific focus on semiconductor foundries About POLYTEDA Software Corporation POLYTEDA Software Corporation is a provider of One Shot DRC processing within its Fine Grain Physical Verification fgPV technology platform which is becoming a critical need for nano scale processes most advanced deep sub wavelength process technologies such us 40nm and below PowerDRC LVS is POLYTEDA s flagship product For more information about POLYTEDA and its products please visit www polyteda com About TekStart TekStart LLC is a leading management consulting and engagement firm based in Las Vegas NV TekStart are experts in the wireless consumer electronics and digital TV markets Originally established in 1997 the team comprises C level

    Original URL path: http://www.polyteda.com/news-a-events/press-releases/153-polyteda-to-expand-global-activities-through-new-joint-alliance-with-tekstart.html?tmpl=component&print=1&layout=default&page= (2016-04-26)
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